CHIP-ARCHITECT






         Sep  20, 2012 The real symmetric representation of the electron and its spin.
         Apr 19, 2012 Ivy Bridge's GPU is 2.25 times as large as Sandy's.

resume Hans
                                          de Vries

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           Sep  4, 2010 AMD's 40nm Bobcat versus Intel's 45nm Atom.
         Aug 10, 2008 The personal work of Hans de Vries.
         Aug 10, 2008 The graduate physics book I'm writing
         Feb 27, 2007 Physics: Electro magnetic propagation in any dimension.
         Feb 27, 2007 Physics: The magnetic field as a relativistic side effect of electro statics.
         Feb 19, 2007 Pretty Pictures of Intel and AMD dies, including process scaling number

Sep 21, 2003 

Understanding the Detailed Architecture of AMD's 64 bit Core

Aug 29, 2003 

Cache efficiency for the SPEC 2000 benchmarks

Aug 22, 2003 

Hot Chips 2003 Coverage

Apr 20, 2003 

Looking at Intel's Prescott die, part II, the prove for Yamhill

Mar 26, 2003 

Intel's Prescott: The clues for Yamhill !

Mar 23, 2003 

Prescott / Nocona doubles number of in-flight instructions

Mar 6, 2003 

Looking at Intel's Prescott die

Jun 24, 2002 

The Two Extra Pipeline Stages of the AMD Hammer

Apr 16, 2002

Intel's Prescott Prospects .

Dec 11, 2001 

Size and Speed of the 130 nm Northwood Pentium 4

Oct 18, 2001 

AMD goes for the performance crown

Oct 7, 2001 

AMD: Long Term Options

Oct 2, 2001 

AMD's 8th generation Hammer processor: A Micro Architecture preview

Nov 25, 2000 

Motorola/AMD's HiP7: A dream process but still a year away

Nov 7, 2000 

Intel's and Motorola/AMD's 130 nm processes to be revealed

Nov 7, 2000 

Speculative Intel adder adds twice as fast 95% of the time

Oct 13, 2000 

An analysis of the newly presented Pentium 4 core.

Oct 10, 2000 

Willamette news and surprises from the Microprocessor Forum.

Sep 27, 2000 

Patents with a new AMD Micro Architecture.

Aug 25, 2000 

Intels Developers Forum

Jun 29, 2000 

Mustang to reach 1.3 GHz debut speeds already at 180 nm

Jun 23, 2000 

News on Willamette's Cache organisation

Jun 2, 2000 

Ashok Kumar mentions 170 mm2 for Willamette's Die size


Jun 1, 2000 

Correction on the Branch Prediction hardware


May 5, 2000 

AMD's Mustang versus Intel's Willamette (PDF)


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address generator
ALU
branch miss prediction penalty
branch prediction
cache
cache hit
cache miss
data cache
dynamic predictor
instruction cache
instruction decoder
instruction pipeline
instruction pre-fetch
instruction sheduler
renamed register file
macro-op
micro-op
predictor selector
processor
processor pipeline

hyper pipelining

hyper threading

simultaneous multi threading
static predictor
trace cache

3dnow
SSE
SSE2

SSE3
MMX
XMM

Athlon

Athlon 64

AMD64
Thunderbird
Spitfire
Duron
Mustang
Corvette

Palomino

Apalona

Thoroughbred

Barton

Sledgehammer
Clawgehammer
Opteron

Pentium 4
Willamette
Foster
Gallatin

Northwood

Prestona

Prescott

Nocona

Jayhawk

Potomac

Tejas

Merom

Conroe

Woodcrest

Kentsfield

Clovertown

Penryn

Changhai

Barcelona

Brisbane

Nehalem
Westmere
Opteron
Deneb

Bulldozer
Bobcat

Trinity
Piledriver

Atom
Core

Hans de Vries
Hans Devries


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