Chip Architect: The personal work of Hans de Vries

August 10, 2008

Resume Hans de Vries

by Hans de Vries

2007-Now: Graduate University textbook on Relativistic Quantum Field Fheory

Some parts of my graduate text book (in progress) are available online:

Understanding Relativistic Quantum Field Theory

Part I Relativistic foundations of light and matter Fields

   Chapter 1: Elementary solutions of the classical wave equation
   Chapter 2:    Lorentz contraction from the classical wave equation
   Chapter 3: Time dilation from the classical wave equation

Chapter 4: Non-simultaneity from the classical wave equation
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Part II Advanced treatment of the EM field

   Chapter 5:    Relativistic formulation of the electromagnetic field
   Chapter 6:    The Chern-Simons EM spin and axial current density
      Chapter 7:    The EM stress energy tensor and spin tensor
   Chapter 8:    Advanced EM treatment of Spin 1/2 fermions

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Part III The relativistic matter wave equations

   Chapter 9: Relativistic matter waves from Klein Gordon's equation
   Chapter 10: The Poincare group and relativistic wave functions
         Chapter 11: The Dirac Equation
   Chapter 12: Transformations of the bilinear fields of the Dirac electron
       Chapter 13:   Gordon decomposition of the vector/axial currents
   Chapter 14: Operators and Observables of the Dirac field
   Chapter 15: The EM interactions with the Dirac field
   Chapter 16: The Hamiltonian and Lagrangian densities

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Part IV Foundations of Quantum Electro Dynamics

Chapter 17: Propagation from the interaction term
Chapter 18: Interference currents from transitions
Chapter 19: Decay rates and Cross sections
Chapter 20: Feynman rules and diagrams of QED
Chapter 21: Elementary QED scattering processes
Chapter 22: Higher order Feynman diagrams

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Part V Non Abelian gauge theories

Chapter 23: The Electroweak theory

Chapter 24: The Electroweak interactions with quarks
Chapter 25: Quantum Chromo Dynamics

2001-2006: Third generation GPGPU stream processor: GenTera MT3 - Imagine 3

As VP of engineering and lead architect I was reponsible for the MT3.
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A third generation GPGPU processor integrating
Streaming SIMD Floating Point cores and
Open GL compatible 3D graphics pipelines with
numerous medical volume rendering extensions,
Fully integrated Video I/O, Audio I/O and legacy IO
- First silicon was achieved in 2006 -

Click on the images for some presentations:

2001-2006 Derivatives of Imagine I

Numerous companies use derivatives of the original Imagine processor
which I designed as the Lead Architect.
One of the latest incarnations is the XTrillion 3.0

- The XTrillion 3.0 is an 8 Core multiprocessor for Medical Applications -

1996 - 2000 Second generation GPGPU stream processor: Arcobel Graphics / GenTera Imagine 2

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The MT2 was our second generation GPGPU processor .
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It had a full hardware implementations of Open GL compatible 3D graphics pipelines.
Advanced Floating point support was added throughout the architecture.
including fully pipelined 32 bit Floating Point Transcendental functions.

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1991-1995 Arcobel Graphics - Imagine 1: Worlds First single chip GPGPU stream processor

As founder and technical director of Arcobel Graphics I was responsible
for the design of the Imagine 1 graphics and Image processor.

- It was the fastest 3D graphics processor on the market when it was released. -

It could both function as a stream processor as well as a
RISC processor executing C code

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1987-1990 DTN: 3D Graphics and Image processing Systollic Array board

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As technical director of Dataflow Technology I designed the
3D graphics and Image processing systolic array board.
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It had a camara input which we used to capture the public during presentations
to show them live texture mapped on moving and rotating 3D graphics objects.
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Up to four boards, each with 4 PCB's could cooperate as a multiprocessing system
with a shared graphics memory of up tp 64 Megabytes which was very
large those days, consisting out of 1024 DRAM and VRAM chips
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http://chip-architect.com/SystollicArrayProcessor.pdf

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1987-1990 DTN: Dataflow processor

1988-1990 Technical Director of Dataflow Technology Nederland

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The company DTN was a management buy out from Philips and its goals

were to develop and commercialize "fifth generation" computers.

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The company was partly funded by governments grants.

Fifth generation computers were a very hot item these days.

There was for the first time a notion that computers would become

large massively parallel processing engines.

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Many often radically different architectures were considered to harness

all the processing power which would become available.

The general expectation was that progress would come from applying new

programming languages, advanced compilers, new computer architectures

together with inter connection systems.

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http://chip-architect.com/DataflowComputer.pdf

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Article about the DTN Dataflow Computer in Dutch

The RC compiler for the DTN dataflow computer

Journal of Parallel and Distributed Computing
Volume 10, Issue 4, December 1990, Pages 319-332

Arthur H. Veen and Reinier Van Den Born

Parallel Computing, Postbus 16775, 1001, RG Amsterdam, The Netherlands

Abstract

The DTN Dataflow Computer is a graphics workstation containing 32 dataflow processing elements. It may possibly be the first commercially available dataflow machine. In this article our main focus is on its RC compiler. Although dataflow machines are usually programmed in a declarative language, RC is imperative: it is a somewhat restricted form of C.

Regards, Hans